jvillarre
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March 2025
Reviewed 9 pull requests in 1 repository
Xilinx/XRT
9 pull requests
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Read data from different segments in buffer for ML Timeline on VE2
This contribution was made on Mar 21
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[XDP] CR-1209911: When 2 PLIOs profiling are requesting on a same interface tile, only one is profiled and no warning are generating
This contribution was made on Mar 21
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[XDP] Enable shim tiles matching using both channelId and streamId.
This contribution was made on Mar 20
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[XDP] remove deprecated metric sets reference.
This contribution was made on Mar 14
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XDP VE2: Resetting timer for all the tiles used in partition and change of core tile trace end event
This contribution was made on Mar 14
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[XDP] Fix overflow conditions of counter indices for large designs
This contribution was made on Mar 12
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[XDP] Prevent segfault by checking correct usage for range of tiles for aie_profile
This contribution was made on Mar 7
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[XDP] Add safe access check for tile stream ids
This contribution was made on Mar 5
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[XDP] Support same tile graph/port latency
This contribution was made on Mar 3