| 🛠️ Project Name | 📦 Repository | 🖼️ Diagram |
|---|---|---|
| Single-Cycle CPU for 31 Instruction Set | Repo |  |
| Single-Cycle CPU for 54 Instruction Set | Repo |  |
| Static Pipelined CPU | Repo |  |
| Dynamic Pipelined CPU | Repo |  |
| Multi-Cycle Pipelined CPU for 89 Instruction Set | Repo |  |
| Porting µC/OS-II to the NEXYS DDR4 Development Board | Repo |  |
- Operating System: 🖥️ Windows 10
- Software Environment: 🛠️ Vivado v2016.2, MARS 4.5, ModelSim PE 10.4c
- Compiler: 📜 Visual Studio Code
- Plugins: 🔌 Github Copilot v1.177.0, Verilog-HDL v1.13.5
- Hardware Device: 🎛️ Nexys 4 DDR Artix-7 FPGA Trainer Board
- IP Core Calls: 📦 Distributed Memory Generator memory (ROM)